CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED ON THREE GATE ELECTRODE TRACKS WITH DIFFUSION REGIONS OF COMMON NODE ON OPPOSING SIDES OF SAME GATE ELECTRODE TRACK

Patent №

US 8,735,995

Granted

2014-05-27

Filed 2013

Owner

Lab

AI components

1

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

13831811

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

AI hardwareH10D 84/907G06F 30/39G06F 30/392G06F 30/398H01L 23/49844H01L 23/5386H10B 10/00H10B 10/10+11 more

AI classification

AI hardware0.69
Vision0.01
Natural language0.01
Planning0.00
Evolutionary computation0.00
Machine learning0.00
Knowledge representation0.00
Speech0.00
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