Patent №
US 10,692,865
Granted
2020-06-23
Filed 2019
Owner
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
16403794
The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.
AI classification
Ownership
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
assignment · 490910451
Assignors
CHING, KUO-CHENG, HSU, TING-HUNG
On an employer assignment, the assignors are typically the inventors.