LOGIC SYNTHESIS SYSTEM COMPRISING A MEMORY FOR A REDUCED NUMBER OF TRANSLATION RULES

In a system which synthesizes a design of a logic circuit from a system input signal representative of an input logical expression of the logic circuit, a memory memorizes fundamental codes and fundamental patterns which are in one-to-one correspondence to the fundamental codes. Responsive to the system input signal, a first code producing arrangement produces a first code corresponding to the input logical expression. Connected to the memory and the first code producing arrangement, a judging circuit judges whether or not the first code is identical with none of the fundamental codes. When the judging circuit judges that the first code is identical with none of the fundamental codes, a second code producing arrangement produces a second code which is a succession of selected ones of the fundamental codes that are selected in accordance with the first code. Connected to the memory, a translating arrangement translates the second code into a translated signal representative of the design with reference to the selected ones of the fundamental codes and selected ones of the fundamental patterns that are in correspondence to the selected ones of the fundamental codes. The translated signal represents a succession of the selected ones of the fundamental patterns. The selected ones of the fundamental codes may be selected from the fundamental codes repetitively. When the first code is identical with one of the fundamental codes, the system is operable like a conventional system.