METHOD AND APPARATUS FOR GATE-LEVEL SIMULATION OF SYNTHESIZED REGISTER TRANSFER LEVEL DESIGN WITH SOURCE-LEVEL DEBUGGING

Register transfer level (RTL) source code is synthesized to generate a gate-level representation and to generate instrumentation logic corresponding to one or more statements in the RTL source code. The instrumentation logic comprises logic circuitry in addition to that of the gate-level representation. The instrumentation logic indicates an execution status for the corresponding RTL statement(s) during gate-level simulation.