METHOD AND APPARATUS FOR ACHIEVING CORRECT ORDER AMONG BUS MEMORY TRANSCATIONS IN A PHYSICALLY DISTRIBUTED SMP SYSTEM

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols. An default order among the commands issued by the plurality of master devices based upon an arrival of a command broadcast by the address switch to the plurality of node controllers and to the plurality of memory subsystems. A snooped command within the set of commands may be reordered or canceled and later reissued.