OPTIMIZING DESIGNING APPARATUS OF INTEGRATED CIRCUIT, OPTIMIZING DESIGNING METHOD OF INTEGRATED CIRCUIT, AND STORING MEDIUM IN WHICH PROGRAM FOR CARRYING OUT OPTIMIZING DESIGNING METHOD OF INTEGRATED CIRCUIT IS STORED

Patent №

US 7,155,685

Granted

2006-12-26

Filed 2003

Owner

SIPEC CORPORATION

+3 more

Lab

AI components

2

planning · evo

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10745648

It is an object of the present invention to provide a method, an apparatus and a program having high optimization precision and capable of obtaining an answer required by a designer in a short time by combining optimization between individual transistors and optimization as the entire circuit, or by appropriately combining judgment of an operation region, an analysis of the operation region and a SWEEP sensitivity analysis when the optimization is carried out. An optimizing designing apparatus of an integrated circuit for designing a circuit, comprises operation region judging means for adjusting an operation region (linear region, saturation region) of the circuit, operation region analysis means for displaying liner characteristics (Ids-Vgs characteristics) of the circuit and saturation characteristics (Ids-Vds characteristics) of the circuit, and SWEEP sensitivity analysis means for displaying variation in output characteristics of the circuit.

AI classification

Planning0.83
Evolutionary computation0.79
Machine learning0.02
Vision0.00
Natural language0.00
AI hardware0.00
Knowledge representation0.00
Speech0.00

Ownership

SIPEC CORPORATION

assignment · 148490349

SEIKO INSTRUMENTS INC.

assignment · 148490349

REALIZE ADVANCED TECHNOLOGY LIMITED

namechg · 203620339

SII SEMICONDUCTOR CORPORATION

assignment · 382250101

Assignors

MORI, KENJI, NAKAJIMA, TAKASHI

On an employer assignment, the assignors are typically the inventors.

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