SYSTEM AND METHOD FOR INTERCOMMUNICATION BETWEEN COMPUTERS IN AN ARRAY

Patent №

US 7,937,557

Granted

2011-05-03

Filed 2004

Owner

TECHNOLOGY PROPERTIES, LTD.

Lab

—

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10801942

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A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

AI hardwareG06F 9/5066G06F 9/5044

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Machine learning0.19

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Natural language0.00

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Ownership

TECHNOLOGY PROPERTIES, LTD.

assignment · 156570652

Assignors

MOORE, CHARLES H.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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Cites (75)

LOOSELY-BIASED HETEROGENEOUS RECONFIGURABLE ARRAYSUS 7,471,643 · 2008 TRANSPARENT DISTRIBUTION AND EXECUTION OF DATA IN A MULTIPROCESSOR ENVIRONMENTUS 7,249,357 · 2007 MANIFOLD ARRAY PROCESSORUS 7,197,624 · 2007 COMMUNICATION REGISTERS FOR PROCESSING ELEMENTSUS 7,162,573 · 2007 PROGRAMMABLE ASYNCHRONOUS PIPELINE ARRAYSUS 7,157,934 · 2007 PARALLEL COMPUTATION PROCESSOR, PARALLEL COMPUTATION CONTROL METHOD AND PROGRAM THEREOFUS 7,136,989 · 2006 SYSTEM AND METHOD FOR GENERATING MULTI-DIMENSIONAL TRACE FILES AND VISUALIZING THEM USING MULTIPLE GANTT CHARTSUS 7,131,113 · 2006 APPARATUS FOR CONTROLLING MULTI-WORD STACK OPERATIONS USING A MULTI-BANK STACK IN DIGITAL DATA PROCESSORSUS 7,028,163 · 2006 PROGRAMMABLE DELAY INDEXED DATA PATH REGISTER FILE FOR ARRAY PROCESSINGUS 6,970,895 · 2005 PROCESSOR CLUSTER ARCHITECTURE AND ASSOCIATED PARALLEL PROCESSING METHODSUS 6,959,372 · 2005 METHOD AND APPARATUS FOR LOOP AND BRANCH INSTRUCTIONS IN A PROGRAMMABLE GRAPHICS PIPELINEUS 6,825,843 · 2004 PROGRAM PRODUCT AND DATA PROCESSORUS 6,826,674 · 2004 SHARED MEMORY TYPE VECTOR PROCESSING SYSTEM, INCLUDING A BUS FOR TRANSFERRING A VECTOR PROCESSING INSTRUCTION, AND CONTROL METHOD THEREOFUS 6,782,468 · 2004 SELECTIVE ENABLING OF DATAPATHS IN SIMD PROCESSOR FOR PROCESSING NON-INTEGRAL MULTIPLE ARRAY DATA IN PLURAL LOOPSUS 6,732,253 · 2004 METHOD AND APPARATUS FOR EMULATING A FLOATING POINT STACK IN A TRANSLATION PROCESSUS 6,725,361 · 2004 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A CIRCUIT FOR CANCELING AN OFFSET VOLTAGE OF AN A/D CONVERTERUS 6,671,112 · 2003 METHOD AND APPARATUS FOR MANAGING ACCESS TO OUT-OF-FRAME REGISTERSUS 6,665,793 · 2003 CONDITIONAL CLOCK BUFFER CIRCUITUS 6,657,462 · 2003 MECHANISM AND METHOD FOR DISTRIBUTING ISUP STACKS OVER MULTIPLE LOOSELY COUPLED PROCESSORSUS 6,507,649 · 2003 PROGRAMMATIC SYNTHESIS OF PROCESSOR ELEMENT ARRAYSUS 6,507,947 · 2003 METHOD FOR JUST IN-TIME DELIVERY OF INSTRUCTIONS IN A DATA PROCESSING SYSTEMUS 6,427,204 · 2002 ASYNCHRONOUS SUPERCONDUCTOR SERIAL MULTIPLY-ACCUMULATORUS 6,388,600 · 2002 FOUR STAGE PIPELINE PROCESSING FOR A MICROCONTROLLERUS 6,353,880 · 2002 METHOD TO DETECT IEEE OVERFLOW AND UNDERFLOW CONDITIONSUS 6,219,685 · 2001 DETECTING AVAILABLE COMPUTERS TO PARTICIPATE IN COMPUTATIONALLY COMPLEX DISTRIBUTED PROCESSING PROBLEMUS 6,192,388 · 2001

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