NESTED CACHE COHERENCY PROTOCOL IN A TIERED MULTI-NODE COMPUTER SYSTEM

Patent №

US 9,727,464

Granted

2017-08-08

Filed 2014

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

Lab

IBM Research

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14549429

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A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.

AI hardwareG06F 12/0824G06F 12/0806G06F 12/0811G06F 12/0815G06F 12/0817G06F 2212/60G06F 2212/621

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Planning0.21

Knowledge representation0.02

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Evolutionary computation0.00

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Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 342270064

Assignors

DRAPALA, GARRETT MICHAEL, LEWIS, WILLIAM J, MAK, PAK-KIN, SONNELITTER, ROBERT J, DRAPALA, GARRETT MICHAEL, LEWIS, WILLIAM J, MAK, PAK-KIN, SONNELITTER, ROBERT J, III

On an employer assignment, the assignors are typically the inventors.

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Cites (13)

CACHE COHERENCY WITHIN MULTIPROCESSOR COMPUTER SYSTEMUS 8,539,164 · 2013 METHOD AND APPARATUS FOR HARDWARE-CONFIGURABLE MULTI-POLICY COHERENCE PROTOCOLUS 8,135,916 · 2012 EFFICIENT PROCESSING OF DATA REQUESTS WITH THE AID OF A REGION CACHEUS 8,055,847 · 2011 METHOD FOR INCREASING CACHE DIRECTORY ASSOCIATIVITY CLASSES VIA EFFICIENT TAG BIT RECLAIMATIONUS 7,925,857 · 2011 METHOD AND SYSTEM FOR ACHIEVING VARYING MANNERS OF MEMORY ACCESSUS 7,904,676 · 2011 METHOD FOR PERFORMING CACHE COHERENCY IN A COMPUTER SYSTEMUS 7,802,058 · 2010 NON-SPECULATIVE DISTRIBUTED CONFLICT RESOLUTION FOR A CACHE COHERENCY PROTOCOLUS 7,434,006 · 2008 SYSTEM AND METHOD FOR LIMITED FANOUT DAISY CHAINING OF CACHE INVALIDATION REQUESTS IN A SHARED-MEMORY MULTIPROCESSOR SYSTEMUS 7,389,389 · 2008 BROADCAST INVALIDATE SCHEMEUS 7,076,597 · 2006 STREAMLINED CACHE COHERENCY PROTOCOL SYSTEM AND METHOD FOR A MULTIPLE PROCESSOR SINGLE CHIP DEVICEUS 6,918,012 · 2005 SHARED MEMORY MULTIPROCESSOR SYSTEM AND METHOD WITH ADDRESS TRANSLATION BETWEEN PARTITIONS AND RESETTING OF NODES INCLUDED IN OTHER PARTITIONSUS 6,510,496 · 2003 CACHE COHERENCY PROTOCOLS WITH GLOBAL AND LOCAL POSTED OPERATIONSUS 6,330,643 · 2001 INTEGRATED PROCESSING AND L2 DRAM CACHEUS 5,895,487 · 1999

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