TRACKING MEMORY ACCESSES WHEN INVALIDATING EFFECTIVE ADDRESS TO REAL ADDRESS TRANSLATIONS

Patent №

US 9,727,483

Granted

2017-08-08

Filed 2015

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

14727075

According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

AI hardwareG06F 12/1009G06F 2212/1016G06F 2212/65G06F 2212/657

AI classification

AI hardware0.58
Natural language0.02
Speech0.00
Planning0.00
Evolutionary computation0.00
Vision0.00
Knowledge representation0.00
Machine learning0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 357550968

Assignors

BLANER, BARTHOLOMEW, HEASLIP, JAY G., LAURICELLA, KENNETH A., STUECHELI, JEFFREY A.

On an employer assignment, the assignors are typically the inventors.

From the same owner

© 2026 NYSGPT2525 LLC