INTEGRATION OF FAULT DETECTION WITH RUN-TO-RUN CONTROL

Patent №

US 7,337,019

Granted

2008-02-26

Filed 2002

Owner

APPLIED MATERIALS, INC.

Lab

AI components

1

planning

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10135405

Semiconductor wafers are processed in conjunction with a manufacturing execution system using a run-to-run controller and a fault detection system. A recipe is received from the manufacturing execution system by the run-to-run controller for controlling a tool. The recipe includes a setpoint for obtaining one or more target wafer properties. Processing of the wafers is monitored by measuring processing attributes including fault conditions and wafer properties using the fault detection system and one or more sensors. Setpoints of the recipe may be modified at the run-to-run controller according to the processing attributes to maintain the target wafer properties, except in cases when a fault condition is detected by the fault detection system. Thus, data acquired in the presence of tool or wafer fault conditions are not used for feedback purposes. In addition, fault detection models may be used to define a range of conditions indicative of a fault condition. In these cases, the fault detection models may be modified to incorporate, as parameters, setpoints of a recipe modified by a run-to-run controller.

PlanningG05B 23/0286G05B 19/41865G05B 2219/31357G05B 2219/31443G05B 2219/45031Y02P 90/02

AI classification

Planning1.00
Knowledge representation0.18
Evolutionary computation0.02
AI hardware0.02
Machine learning0.01
Natural language0.00
Speech0.00
Vision0.00

Ownership

APPLIED MATERIALS, INC.

assignment · 128730543

Assignors

REISS, TERRY P., SHANMUGASUNDRAM, ARULKUMAR P., SCHWARM ALEXANDER T.

On an employer assignment, the assignors are typically the inventors.

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